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System-on-chip test architectures : ...
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ScienceDirect (Online service)
System-on-chip test architectures : nanometer design for testability
紀錄類型:
書目-語言資料,印刷品 : 單行本
副題名:
nanometer design for testability
其他作者:
StroudCharles E.,
其他作者:
ToubaNur A.,
其他作者:
WangLaung-Terng.,
其他團體作者:
ScienceDirect (Online service)
出版地:
Amsterdam
出版者:
Morgan Kaufmann Publishers;
出版年:
c2008.
面頁冊數:
xxxvi, 856 p.ill. : 25 cm.;
集叢名:
The Morgan Kaufmann series in systems on silicon
標題:
Integrated circuits - Very large scale integration -
標題:
Integrated circuits - Very large scale integration -
標題:
Systems on a chip - Testing. -
標題:
Electronic books. -
電子資源:
http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
電子資源:
http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
電子資源:
http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
電子資源:
http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
附註:
Electronic reproduction. Amsterdam : Elsevier Science & Technology, 2008.
摘要註:
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.
ISBN:
012373973X
內容註:
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
System-on-chip test architectures : nanometer design for testability
System-on-chip test architectures
: nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. - Amsterdam : Morgan Kaufmann Publishers, c2008.. - xxxvi, 856 p. ; ill. ; 25 cm.. - (The Morgan Kaufmann series in systems on silicon).
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends..
Electronic reproduction. Amsterdam : Elsevier Science & Technology, 2008..
Includes bibliographical references and index..
ISBN 012373973XISBN 9780123739735
Integrated circuits Integrated circuits Systems on a chip Electronic books. -- Very large scale integration -- Very large scale integration -- Testing.
Stroud, Charles E.
System-on-chip test architectures : nanometer design for testability
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