The designer's guide to VHDL
Ashenden, Peter J.

 

  • The designer's guide to VHDL
  • 紀錄類型: 書目-語言資料,印刷品 : 單行本
    作者: AshendenPeter J.,
    其他團體作者: ScienceDirect (Online service)
    出版地: Amsterdam
    出版者: Morgan Kaufmann Publishers;
    出版年: c2008.
    版本: 3rd ed.
    面頁冊數: xxii, 909 p.ill. : 25 cm.;
    集叢名: The Morgan Kaufmann series in systems on silicon
    標題: Electronic digital computers - Computer simulation. -
    標題: VHDL (Computer hardware description language) -
    標題: Electronic books. -
    電子資源: http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780120887859
    電子資源: http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780120887859
    附註: Electronic reproduction. Amsterdam : Elsevier Science & Technology, 2008.
    摘要註: VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008. * First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard. * Presents a structured guide to the modeling facilities offered by VHDL...shows how VHDL functions to help design digital systems. * Includes extensive case studies and source code used to develop testbenches and case study examples..helps readers gain maximum facility with VHDL for design of digital systems.
    ISBN: 0120887851
    內容註: Fundamental Concepts Scalar Data Types and Operations Sequential Statements Composite Data Types and Operations Basic Modeling Constructs Case Study: A Pipelined Complex Multiplier Accumulator Subprograms Packages and Use Clauses Aliases External Names in Testbenches Properties and Assertion-Based Design Resolved Signals Generics Components and Configurations Generate Statements Access Types and Abstract Data Types Files and Input/Output Case Study: Queuing Networks Attributes and Groups Design for Synthesis Case Study: System Design using the Gumnut Core Miscellaneous Topics Standard Packages Related Standards VHDL Syntax Differences Among VHDL Versions Answers to Exercises References Index.
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